A conventional semiconductor package, such as Quad Flat Package(QFP) or Quad Flat Non-leaded(QFN) package, uses a lead frame as a chip carrier having a die pad and a plurality of leads, allowing at least one chip to be mounted on the die pad and electrically connected to the leads by a plurality of bonding wires which are bonded to bond pads on a surface of the chip. An encapsulation body is adopted to encapsulate the chip, the lead frame, and the bonding wires to thereby form the semiconductor package. Moreover, the die pad can be made to have one surface thereof exposed to outside of the encapsulation body, and such an exposed-pad type package facilitates dissipation of heat from the chip via the exposed surface of the die pad.
In response to improvement in chip integration, for the sake of enhancing the electricity performance and reducing noise, the semiconductor package is preferably made to provide grounding function for the chip incorporated therein, which can be accomplished by connecting ground wires to the die pad of the lead frame to effect the grounding performance. However, since the ground wires are usually bonded to peripheral areas on the die pad, in the case of delamination occurring between the die pad and the encapsulation body due to mismatch in coefficient of thermal expansion (CTE) thereof, the ground wires tend to break easily and degrade the electricity performance. Such a drawback becomes more severe in an exposed-pad type package where the occurrence of delamination between the die pad and the encapsulation body is increased due to relatively weaker adhesion therebetween.
Accordingly, U.S. Pat. Nos. 5,196,725, 5,237,202, 5,399,809, 5,734,198 and 5,777,265 disclose a semiconductor package using a multi-layer lead frame which is formed with a ground plane, for allowing ground wires to be electrically connected to bond pads on a chip, so as to reduce noise for the chip. However, such a multi-layer lead frame is rather complex in structure which is not material-effective to fabricate, thereby leading to a burden for manufacture and costs of the semiconductor package as well as not in favor of large-scale production.
Therefore, U.S. Pat. No. 5,814,877 provides a single-layer lead frame which is cost-effective and simple to fabricate and not affected by the die-pad delamination problem, wherein a ground ring 62 is formed around a die pad 61 of the lead frame 60 and electrically connected to ground pads on a chip 63, as shown in FIGS. 5A and 5B. Moreover, for an exposed-pad type package, a ground ring can be separate from the die pad and is thus not damaged by the occurrence of delamination between the die pad and the encapsulation body; as shown in FIGS. 6A and 6B, the lead frame 70 taught by U.S. Pat. No. 6,437,427 is formed with a ground ring 73 separate from the die pad 71, such that ground wires 75 not connected to the die pad 71 would not break by delamination of the die pad 71. FIGS. 7A and 7B show another semiconductor package having ground ring according to U.S. Pat. No. 6,380,048, in which a ground ring 82 surrounds the die pad 81 of the lead frame 80 and is connected by S-shaped tie bars 83 to the die pad 81 in a manner that, symmetric hollow-out portions 84 of a predetermined shape are arranged between the die pad 81 and the ground ring 82 and facilitate the release of thermal stresses generated during molding; also, the hollow-out portions 84 are filled by an encapsulation body 85 by which the lead frame 80 is more strongly held in position.
Although the above ground ring desirably simplifies fabrication processes, reduces costs and prevents breaks of ground wires, its continuous ring structure would be easily deformed in a high-temperature condition such as die bond curing, wire bonding and molding processes and reliability tests, as shown in FIGS. 8A and 8B. This thermal deformation is caused by thermal expansion of metallic material making the ground ring which is constrained within or not able to be released from the continuous ring structure, and thereby damages the planarity of the ground ring. The deformed ground ring also increases the difficulty in bonding the ground wires, or the ground wires may subject to breaking by the deformation, making the electricity performance undesirably degraded. Besides, during a stamping process for fabricating the lead frame having the continuous ground ring, the stamping force may be left to form residual stresses in the ground ring, which also leads to deformation of the ring structure under a subsequent high-temperature environment.
In respect of FIGS. 7A and 7B taught by U.S. Pat. No. 6,380,048, although the S-shaped tie bars 83 may release the thermal stresses generated during molding, the released stresses are merely from the S-shaped tie bars 83 which interconnect to the die pad 81 and the ground ring 82. The hollow-out portions 84 provides space for stress release from the tie bars 83 along the directions indicated by arrows shown in FIG. 9A. However, for the ground ring 82 whose periphery is tied by the tie bars 83, the thermal stresses are not allowed to be easily released from the ground ring 82, and as a result, the ground ring 82 would be deformed as shown in FIG. 9B, further causing damage to the electrical connection or breaking g (as circled in FIG. 9C) of ground wires 86. Namely, the provision of the S-shaped tie bars still fails to solve the problem of ground-ring deformation.
Therefore, it is of great interest to develop a ground-enhanced semiconductor package that prevents deformation of ground areas and breaks of ground wires under a high-temperature fabricating condition to ensure the electricity performance thereof.